Engineer Digital
Title :
Engineer Digital
Duration :
6 Months Contract
Location :
Azusa, CA
Job Description:
- Remote Position
- Bachelor's degree required
- Minimum of 5yrs writing SystemVerilog and UVM as a primary job function
- Experience with verification of designs written in VHDL
- Experience with Linux command line workflows
- Experience writing TCL to control verification tools
- Demonstrated ability in root-cause analysis of test failures
- Experience working closely with RTL designers to collaboratively resolve verification test failures
- Experience with Git S
- CM using LFS and Submodules
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